The present invention relates generally to a ramp generator for analog-to-digital (A/D) conversion applications and more particularly to a programmable non-linear ramp generator which utilizes a switched-capacitor array for A/D conversion applications.
An analog-to-digital converter (ADC) may be used to translate an analog signal (e.g., a current or voltage produced by a sensor) into a digital signal that can be used by another device (for example, a microprocessor). In complimentary metal-oxide semiconductor (CMOS) imaging applications, for example, ADCs are increasingly being used as the preferred means for converting charge captured by CMOS sensors into a digital read-out.
Several types of ADCs are currently used, each type differing in the technique utilized to complete the A/D conversion. For example, feed-back type converters, dual-slope converters, flash converters, charge-redistribution converters, and digital ramp converters are known in the art.
A feedback-type converter typically employs a comparator, an up-down counter, and a digital-to-analog converter (DAC). FIG. 8 is a simplified diagram of a prior art feedback-type converter. An analog signal (VA) is fed to one input of the comparator. The output of the comparator is connected to the input of the counter. The outputs of the counter are connected to the inputs of the DAC and the output of the DAC (Vo) is fed back to another of the comparator's inputs. The counter also receives a clock signal. Whenever the output of the comparator is high (i.e., when the difference between VA and Vo is positive), the counter counts the pulses of the clock signal and the output of the counter increases. This in turn causes the voltage Vo to rise. When Vo equals VA, the output of the comparator goes low and the counter is stopped. At this point, the counter's output represents the digital equivalent of the analog signal voltage.
FIG. 9 is a simplified diagram of a prior art dual-slope converter. A dual-slope converter typically functions in two stages. In the first stage, an analog signal (VA) is applied for a fixed time period to charge the capacitor C1 and produce a voltage v1. The voltage v1 typically has a variable slope during this first stage. In the second stage, a reference signal (Vref) is applied for a variable time period and allows the voltage v1 to discharge from the capacitor C1. The voltage v1 typically has a constant slope during the second stage. Control logic provides signals to control switching between the first and second stages. The control logic also provides control signals to a counter which is used to count pulses from a fixed-frequency clock. The count recorded by the counter during the second stage represents the digital equivalent of the analog voltage applied during stage 1.
FIG. 10 is a simplified diagram of a prior art flash converter. A flash converter typically uses 2N-1 comparators to simultaneously compare the analog input signal level (VA) to each of the 2N-1 possible quantization levels. A 4-bit DAC, for example, uses sixteen comparators to convert an analog signal into a 4-bit digital word. The DAC includes a logic block that encodes the output from each of the sixteen comparators into the N-bits of the digital word. For instance, an analog input signal between 0 and 5V may be represented using the 4-bit binary number. The 4-bit binary number may represent 24 (i.e., 16) different values (i.e., from 0 to 15). The resolution of the conversion will thus be 5V/15=⅓V. Accordingly, the first quantization level (e.g., for bit 0000) corresponds to an analog signal of 0V, the second quantization level (e.g., for bit 0001) corresponds to an analog signal of ⅓V, the third quantization level (e.g., for bit 0010) corresponds to an analog signal of ⅔V, and so on. This pattern is repeated for each of the sixteen quantization levels (i.e., up to bit 1111, which corresponds to an analog signal of 5V).
FIG. 11 is a simplified diagram of a prior art charge-redistribution converter. A charge-redistribution converter typically uses a capacitor array, a comparator, switches, and control logic, among others. During operation, a voltage (vA) proportional to the analog input voltage (VA) is first stored across the capacitors in the capacitor array by connecting one side of the array to VA and the other side of the array (e.g., the side also connected to an input of the comparator) to ground. The plates of capacitors connected to the input terminal of the comparator are then open-circuited (e.g., switch S2 is opened) while the plates of the capacitors on the other side of the capacitor array are switched to ground (e.g., SC1, SC2, . . . SC6 are connected to ground). Next, the charge stored by the capacitors is redistributed by switching the individual capacitors to the reference voltage and/or ground until the voltage across the plates of the capacitors reaches zero. The final position of the switches (i.e., SC1, SC2, . . . SC6) represents the output of the digital word. For example, a switch that is connected to ground in its final position represents a “0”; whereas a switch connected to the reference voltage source in its final position represents a “1”.
A digital ramp converter typically includes a comparator and a ramp generator. An analog signal is fed to one input of the comparator and the output of the ramp generator is fed to another input of the comparator. FIG. 12 is a simplified circuit diagram of a ramp generator 100 and a comparator 102 according to the prior art. FIG. 13 is a timing diagram for a ramp generator 100 of FIG. 12 according to the prior art. The ramp generator 100 is comprised of a plurality of identical switching current sources 101(1), 101(2), 101(3), . . . 101(n), a capacitor 103, and reset switch S0. Operation begins by placing the ramp generator 100 into the reset mode by opening switches S1, S2, S3, . . . Sn and closing switch S0. Referring to FIG. 13, at to, signal To goes high and signals T1 through Tn remain low (which keep switches 101(1) through 101(n) open). When signal T0 goes high, switch S0 is closed and the output of the ramp generator 100 is connected to the voltage source Vref (i.e., Vramp equals Vref).
At t1, signal T0 goes low opening switch S0 and signal T1 goes high closing switch S1 and enabling current source 101(1). Current source 101(1) charges capacitor 103 and the output of the ramp generator (i.e., Vramp) begins to rise above Vref at a constant rate which is proportional to the value of the current source 101(1). At the first break point, t2, signal T2 goes high closing switch S2 and enabling current source 101(2). The slew rate of the ramp generator output is now doubled. At the next break point, t3, signal T3 goes high closing switch S3 and enabling current source 101(3). This increases the slew rate of the ramp generator again. The final break point occurs at tn when the last current source 101(n) is enabled by signal Tn closing switch Sn.
Returning to FIG. 12, the output of the ramp generator (i.e., Vramp) is supplied to an input terminal comparator 102. Comparator 102 compares Vramp with an analog signal Va, which is supplied to another input terminal of the comparator 102. If Va is greater than Vramp, the output of comparator 102 is high and the ramp generator 100 continues to increase Vramp. If Vramp is greater than Va, the output of the comparator 102 goes low and the ramp generator 100 stops increasing Vramp. An ADC code counter (not shown) is used to stop the ramp and to determine the ADC code.
One major drawback inherent to prior art ramp generators 100, however, is the difficulty encountered in trying to manufacture matched current generators. Due to the manufacturing techniques used to construct the transistors comprising the current sources, a current source can typically only be matched within approximately 2% of another current source. The inability to accurately match current source leads to inaccurate conversion of the analog signal.
As discussed above, ADCs are increasingly being used as the preferred means for converting charge captured by CMOS sensors into a digital read-out in CMOS imaging applications. The error inherent in the prior art ADCs adversely effects the results obtained in the CMOS imaging applications.
Accordingly, a need exists for a modulating ramp A/D converter which overcomes these problems and which overcomes other limitations inherent in the prior art. More specifically, a need exists for a modulating ramp A/D converter which can be used in CMOS imaging applications, for example, to convert charge captured by CMOS sensors into a digital read-out.